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CXA2019AQ
NTSC/PAL Chroma Decoder
Description The CXA2019AQ is a bipolar IC which integrates the luminance signal processing, chroma signal processing, and sync signal processing functions for NTSC/PAL system color TVs onto a single chip. Features * Sub picture bright and white balance can be adjusted by using the main picture Y/C/J BGP output as the timing pulse * I2C BUS compatible; two bus lines (SCL, SDA) allow various adjustments and user controls * Countdown system eliminates need for H and V oscillator frequency adjustment * Non-adjusting Y system filters (chroma trap, delay line) * Automatic identification of color system (forced control possible) * Automatic identification of 50/60Hz vertical frequency (forced control possible) * Built-in delay line aperture correction * Built-in dynamic picture (black expansion) function * Combination with a non-adjusting SECAM chroma decoder allows configuration of multiple systems Absolute Maximum Ratings (Ta = 25C, SGND, JGND = 0V) * Supply voltage VCC 12 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1.67 W Operating Conditions Supply voltage 40 pin QFP (Plastic)
Applications Color TVs Structure Bipolar silicon monolithic IC
VCC
9 0.5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E98320-PS
Block Diagram
J Vcc SCP AFC V SYNC V TIM V HOLD V2 OUT U2 OUT CERA H TIM Y2 OUT
8 U2 PED Y2 DRIVE ABL CENT U2 DRIVE
ADRS
SDA
SCL
IREF
35 16 V2 PED 32fH VCO ABL PHASE DET. 1/32 Y2 DRIVE U2 PED AFC HLOCK V2 PED V2 DRIVE C MODE 50/60 U2 DRIVE 12 U2 IN 13 V2 IN 11 Y2 IN 2fH H.DRIVE V.SYNC SEP V COUNT DOWN 9 ABLFILIN V2 DRIVE 14
37 3 2 7 1 38 40 15 6
36
4
39
H SYNC
I2C BUS DECORDER
IREF
H.SYNC SEP
J GND
5
CV/YC DELAY TRAP ON PRE OVER DC TRAN Y DRIVE U PED SHARPNESS V PED
SHP f0
SUB CONT
SECAM
10 CP IN The sub picture bright and white balance can be adjusted by receiving BGP or SCP output from the main picture Y/C/J, clamping the PINP PROC. output, and varying the DC of the clamped portion. 17 SGND2
CVBS/Y IN 34 DELAY CLAMP Y DRIVE SHARPNESS AUTO PEDESTAL
SVCC
APC
X 358
X 443/358
X NTSC
A PED
- (B_Y) IN
- (B_Y) OUT
- (R_Y) IN
SECAM REF
- (R_Y) OUT
-2-
NT/PAL SUB HUE NT/PAL HUE PAL ID F.F ID AXIS COLOR PHASE DET. DEM AXIS HUE LPF CHROMA VCO X'TAL PIN 26 33 23 24 PHASE SHIFT CHROMA DET. COLOR 2fH DET SW CLAMP 22 21 4.43/3.58 SW 29 28 27
CIN 32
VIDEO SW
SUB CONT
TRAP
TRAP 18 Y OUT 19 U OUT U PED V PED 20 V OUT
SUB COLOR
ACC
ACC DET.
TOT ON
TOT
BST AMP
DELAY
COLOR KILLER
S GND 31
KILLER
SECAM
NT/PAL EXT COLOR
30
25
CXA2019AQ
CXA2019AQ
Pin Configuration
SECAM REF
- (R_Y) OUT
- (B_Y) OUT
- (B_Y) IN
22
X NTSC
APC
30
29
28
27
26
25
24
23
21
S GND 31 CIN 32 A PED 33 CVBS/Y IN 34 ADRS 35 SCL 36 SDA 37 V SYNC 38 H SYNC 39 V HOLD 40
- (R_Y) IN
X 443/358
X 358
SVCC
20 V OUT 19 U OUT
18 Y OUT 17 SGND2 16 15 14 SCP H TIM V TIM
13 V2 IN 12 U2 IN
11 Y2 IN
1
2
3
4
5
6
7
8
9
10
U2 OUT
Y2 OUT
J GND
CERA
-3-
ABLFILIN
V2 OUT
CP IN
AFC
IREF
JVCC
CXA2019AQ
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
Vcc Vcc Vcc 10k 28k 1
Description
1
CERA
--
32fH (500 or 503.5kHz) ceramic oscillator connection.
Vcc
Vcc
Vcc
2
AFC
--
2 1.2k 46k
CR connection for AFC lag-lead filter.
3
JVCC
9.0V
Power supply.
Vcc
4
IREF
1.8V
4 150
20k 14.4k
Connect a 10k resistor between this pin and GND.
5
J GND
--
Vcc 200
Jungle system (H/V) GND.
6 7
V2 OUT U2 OUT
Vcc
3V
6 7 8.6k 20k
Reinput system outputs.
Vcc Vcc 200 Vcc 4k
8
Y2 OUT
3V
8 8k
Reinput system output.
-4-
CXA2019AQ
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
Vcc
Vcc
9
ABLFILIN
--
9
37k 90k 90k
ABLFIL voltage input. Input the main picture Y/C/J ABLFIL voltage.
Vcc Vcc 15k
10
CP IN
--
10 1.2k
Reinput system clamp pulse input. Input the main picture BGP (SCP). Vth: 2.5V
Vcc 11
11 12 13
Y2 IN U2 IN V2 IN
4V
12 13 1.2k 70k
Reinput system inputs. Input via a capacitor.
Vcc Vcc 1k
14
V TIM
--
14 20k 1k
V timing pulse output. Outputs a 0 to 5V positive polarity pulse.
Vcc Vcc 1k
15
H TIM
--
15 20k 1k
H timing pulse output. Outputs a 0 to 5V positive polarity pulse.
-5-
CXA2019AQ
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
Vcc Vcc 1.2k
Vcc
Outputs BGP and HBLK as SCP (sand castle pulse). The typ. waveform is as follows.
16
SCP
--
16 500A HBLK BGP
5.0V 2.0V 0.3V
17
SGND2
--
Vcc 200 Vcc
GND.
18
Y OUT
3V
20k 18 6k
Y (luminance signal) output. Standard output level: 1.1Vp-p
Vcc 200 Vcc
19 20
U OUT V OUT
3V
19 20 8.6k
20k
U/V (color difference signal) outputs. Output level: U = V = 1.2Vp-p (In case of setting data as shown in "I2C BUS Register Initial Settings.")
Vcc 21 22 1.2k
Vcc
21 22
- (R_Y) IN - (B_Y) IN
Color difference signal inputs. Input as negative polarity via a capacitor.
70k
5.6V
BGP 100A
Standard input levels: B-Y: 1.33Vp-p R-Y: 1.05Vp-p
-6-
CXA2019AQ
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
Vcc Vcc 23
Vcc
23 24
Color difference signal outputs. Output as negative polarity. Standard output levels: B-Y: 0.665Vp-p R-Y: 0.525Vp-p
- (B_Y) OUT - (R_Y) OUT
5.6V
24
1.2k
25
SVCC
9.0V
Vcc
Power supply.
4k
26 27 28
X NTSC X 358 X443/358
Vcc
--
26 27 28 500
Crystal oscillator connections. Connect the PALN and 4.43MHz crystal to Pin 28. Connect the PALM crystal to Pin 27, and the NTSC crystal to Pin 26.
Vcc Vcc 1.2k
29
APC
--
29 1.2k 25k
CR connection for APC lag-lead filter.
Vcc Vcc 6k 10p
Vcc
30
SECAM REF
1.5V
30 40k
When the IC is set to SECAM identification mode, the 4.43MHz VCO oscillator waveform is output from this pin centering on DC 1.5V. If a 150A current is led from this pin during this identification mode, the IC is set to SECAM mode. In SECAM mode, the 4.43MHz VCO oscillator waveform is output centering on DC = 5V only during the VBLK interval. GND.
31
S GND
--
-7-
CXA2019AQ
Pin No.
Symbol
Pin voltage
Equivalent circuit
Vcc 10p 32 30k 30k
Description
Chroma signal input. Standard input level (burst level) : 570mVp-p
32
C IN
--
Vcc Vcc
Vcc
Vcc
33
A PED
--
33
16k 20k
20k 1.2k
Black peak hold for auto pedestal (black expansion). Connect a capacitor.
Vcc 1.2k 34
Vcc 1.2k
70k
Y signal input. Input via a capacitor. 34 CVBS/Y IN -- Standard input level: 2Vp-p
1.2k
Vcc
35
ADRS
--
35 77k 30k
This pin is used to switch the slave address. Vcc: 9AH GND: 9EH Vth = 2.5 V
-8-
CXA2019AQ
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
Vcc
36 37
SCL SDA
--
36 37
4k
4k
I2C BUS SCL (Serial Clock) and SDA (Serial Data). Vilmax = 1.5V Vihmin = 3V Volmax = 0.4V
Vcc
15k
24k
38
V SYNC
3.5V
150 38 20A 33k
V sync separation input. Input a 2Vp-p video signal via a capacitor and resistor.
Vcc
14k
24k
39
H SYNC
2.5V
150 39 10A 20k
H sync separation input. Input a 2Vp-p video signal via a capacitor and resistor.
55k Vcc
40
V HOLD
--
40
150
1k 50k
Peak hold for V sync separation. Connect a capacitor.
-9-
Electrical Characteristics Setting conditions * Ta = 25C, SVCC = JVCC = 9V * Measures the following after setting the I2C bus register as shown in "I2C BUS Register Initial Settings".
Measurement conditions Measurement contents Measure the pin inflow current. 46 68 94 Min. Typ. Max. SVCC = JVCC = 9V 3, 25 Measurement pins Unit mA
No.
Item
Symbol
1
Current consumption
ICC
H system items 15 HTIM output frequency 15.50 15.65 15.85 kHz
2
Horizontal free-running frequency
fH
3 AFC: 0 15
Horizontal sync pull-in range
fH
Confirm that I2C bus register HLOCK is 1 (the pull-in range when fH is shifted from 15.734kHz). -400 9.3
400
Hz
4 15
HTIM-H HTIM-L HTIM-W
HTIM output pulse width
HTIM-W
9.9 4.5 0.0 9.6 4.85 0.1 10.5
10.4 5.1 0.5 11.2
s V V s
5
HTIM output high level
HTIM-H
- 10 -
16 SCP BGR: 1 SCP BGF: 1 AFC: 0 SYNCIN: SIG-H3/SIG-H4 AFC: 1 SYNCIN: SIG-H3/SIG-H4 15 AFC: 2 SYNCIN: SIG-H3/SIG-H4
SIG-H3, H4 t
6
HTIM output low level
HTIM-L
7
SCP BLK output pulse width
SBLK-W
SBGP-W SBLK-W
8
SCP BGP output pulse width
SBGP-W
3.2
3.8 0.4 0.6 t = t (SIG-H3) - t (SIG-H4) 1.2
4.3
s s s s
9
AFC gain 1
t1
10
AFC gain 2
t2
11
AFC gain 3
t3
CXA2019AQ
No. Measurement conditions Measurement contents Min. Typ. Max. Unit
Item
Symbol
Measurement pins
V system items VFREQ: 0 14 VTIM output frequency (for 60Hz mode) 4.7 5.0 0.2 50
VTIM-L
12 60 5.3 0.5 55 14
VTIM-H
Vertical free-running frequency 1 55 65
fV1
Hz V V Hz
13 14 VFREQ: 1 14 VTIM output frequency (for 50Hz mode) 45 0.0
VTIM output high level
VTIM-H
14
VTIM output low level
VTIM-L
15
Vertical free-running frequency 2
fV2
YUV system items
HTIM
16 U PED: 1F V PED: 1F 19
U/V OUT Vclamp Vped. 1, 2
U/VOUT clamp
Vc1amp
2.7 5 -15 2.7 32
Vrclamp
3.0 10 -8 3.0 45
3.2 16 -4 3.2 57 -41 -13
V mV mV V mV mV
17 20 U PED: 0 V PED: 0 CP IN: SIG-H5 (Normally input when reinput system is measured)
SIG-H5
U/VOUT pedestal variation 1
Vped1
- 11 -
U2 PED: 1F V2 PED: 1F 6 7 U2 PED: 0 V2 PED: 0 Y2 IN: SIG-Y1 Y2 DRIVE: 1F 8 Gy2dr = 20 log Y2 IN: SIG-Y1 Y2 DRIVE: 0
Vx U2/V2OUT Vrped. 1, 2
18
U/VOUT pedestal variation 2
Vped2
19
U2/V2OUT clamp
Vrc1amp
20
U2/V2OUT pedestal variation 1
Vrped1
21
U2/V2OUT pedestal variation 2
Vrped2
-27 2.3 -4.9 2.8 -4.0
22
Y2 DRIVE variable range 1
Gy2dr1
3.3 -3.3
dB Vx (Y2 DRIVE: 1F/0) Vx (Y2 DRIVE: F) dB
23
Y2 DRIVE variable range 2
Gy2dr2
24
U2/V2 DRIVE variation 1
Grdr1
U2/V2 IN: SIG-Y1 U2 DRIVE: 1F V2 DRIVE: 1F
Vx
2.8 6 7 Grdr = 20 log Vx (U2/V2 DRIVE: 1F/0) Vx (U2/V2 DRIVE: F) -8.0
3.6
4.4
dB
CXA2019AQ
25
U2/V2 DRIVE variation 2
Grdr2
U2/V2 IN: SIG-Y1 U2 DRIVE: 0 V2 DRIVE: 0
-6.3
-4.5
dB
No. Measurement conditions Measurement contents Min. Typ. Max. Unit
Item
Symbol
Measurement pin
Y system items Y IN: SIG-Y2 Y DRIVE: F 0.9 1.1 3.5 -6.3 3.5 7.6 -6.3 -5.2 4.2 -5.7 4.2 8.3 -4.1 1.3
Vx
26 Y IN: SIG-Y2 Y DRIVE: 1F 18 Vyout = Vx (Y DRIVE: F) Vx (Y DRIVE: 1F/0) Gydr1, 2 = 20 log Vx (Y DRIVE: F) -6.9 2.8
Vx
Y OUT output amplitude 2.8
Vyout
V dB dB dB dB dB
27 Y IN: SIG-Y2 Y DRIVE: 0 Y IN: SIG-Y3 SHARPNESS: 7 Y IN: SIG-Y3 SHARPNESS: F 18 Gshr1, 2 = 20 log Vx (f = 3MHz) Vx (f = 100kHz) Y IN: SIG-Y3 SHARPNESS: 0 Y IN: SIG-Y2 SUB CONT: F
Vx
Y DRIVE variable range 1
Gydr1
28
Y DRIVE variable range 2
Gydr2
29 6.8
SHARPNESS center
Gshr
30
SHARPNESS variable range 1
Gshr1
31
SHARPNESS variable range 2
Gshr2
- 12 -
18 Y IN: SIG-Y2 SUB CONT: 0 Gsc1, 2 = 20 log
Vx
32
SUB CONT variable range 1
Gsc1
1.9
2.4
2.9
dB
33
SUB CONT variable range 2
Gsc2
Vx (SUB CONT: F/0) Vx (SUB CONT: 7)
-3.5
-3.1
-2.7
dB
34 Y IN: SIG-Y4 18
Y OUT frequency response
fyout
-3.0 fyout = 20 log Vx (f = 8MHz) Vx (f = 100kHz)
Vx
-0.5
2.2
dB
35
C-TRAP attenuation 358
C-trap1
Y IN: SIG-Y5 TRAP SW: 0/1 CTRAPADJ: adjustment value Y IN: SIG-Y6 TRAP SW: 0/1 CTRAPADJ: adjustment value
18
-35
-25
dB
36
C-TRAP attenuation 443
C-trap2
18
C-trap = 20 log
Vx (TRAP SW: 1) Vx (TRAP SW: 0)
-35
-25
dB
CXA2019AQ
No. Measurement conditions Measurement contents Min. Typ. Max. Unit
Item
Symbol
Measurement pin
C system items
37 C IN: SIG-C1 (No.37 to 42) 19 1.2 0.9 1.5
UOUT output amplitude Vuout
Vx
V
38 C IN: SIG-C2 (No.37 to 42) 20 0.9
VOUT output amplitude
Vvout
Vx
1.2
1.5
V
39 COLOR: 3F COLOR: 0 SUB COLOR: F 19 20 SUB COLOR: 0 -- CVBS: burst only During NTSC input -- -- Confirm that the burst frequency is pulled in at 3.58MHz 400Hz. Vx (SUB COLOR: F/0) Gscol1, 2 = 20 log Vx (SUB COLOR: 7) 19 20 Gcol1, 2 = 20 log Vx (COLOR: 3F/0) Vx (COLOR: 1F)
COLOR variable range 1
Gcol1
5.8
6.3
6.8 10 2.1 2.7 3.3
dB mV dB
40
COLOR variable range 2
Gcol2
41
SUB COLOR variable range 1
Gscol1
42
SUB COLOR variable range 2
Gscol2
-5.0 -11
-3.6 -3 -33 -400
-2.3 5
dB deg dB 400 Hz
- 13 -
43
HUE center offset
offset
44
Killer point
KP
45
APC pull-in range
fAPC
CXA2019AQ
CXA2019AQ
I2C BUS System Items No. Item Symbol Vih Vil lih lil Vol lol Ci fscl tbuf thd;sta tlow thigh tsu;sta thd;dat tsu;dat tr tf tsu;sto Min. 3.0 0 -- -- 0 3 -- 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 10 10 0.4 -- 10 100 -- -- -- -- -- -- -- 300 300 -- Unit V V A A V mA pF kHz s s s s s s ns ns ns s
46 High level input voltage 47 Low level input voltage 48 High level input current 49 Low level input current Low level output voltage 50 During current inflow of 3 mA to SDA (Pin 37) 51 SDA inflow current 52 Input capacitance 53 Clock frequency 54 Minimum waiting time for data change 55 Waiting time for data transfer start 56 Low level clock pulse width 57 High level clock pulse width 58 Waiting time for start preparation 59 Data hold time 60 Data preparation time 61 Rise time 62 Fall time 63 Waiting time for stop preparation
- 14 -
CXA2019AQ
Electrical Characteristics Measurement Circuit
9V PAL PAL/M NTSC 0.47 15k 470p 30 29 28 470 27 1.5k 26 1.5k 25 24 23 22 1 21 1 15p 15p 0.01 15p 47
SECAM REF
- (R_Y) OUT
X 358
- (B_Y) IN
X 443/358
SVCC
31 S GND CIN 32 CIN
- (B_Y) OUT
- (R_Y) IN
X NTSC
APC
V OUT 20
V output
U OUT 19
U output
33 A PED Composite video input YIN 4.7 34 CVBS/Y IN 0.47 35 ADRS 9V or 0V 36 SCL I2C bus input/output 100 37 SDA 100 38 V SYNC 2.2k 3.3k SYNCIN 100 1 39 H SYNC 220 4700p 0.47 40 V HOLD
Y OUT 18
Y output
SGND2 17
SCP 16
SCP output
H TIM 15
H TIM output
V TIM 14
V TIM output
V2 IN 13 1 V2 IN U2 IN 12 1 U2 IN
V2 OUT
Y2 OUT
ABLFILIN
U2 OUT
J GND
CERA
JVCC
IREF
CP IN
Y2 IN 11 1 Y2 IN
100p 330k 330 500kHz ceramic oscillator
AFC
1 0.01
2 8.2k 1 47
3 10k
4
5
6
7
8
9
10 CPIN
V2 U2 Y2 output output output 0.01 9V
ABL voltage
- 15 -
CXA2019AQ
Application Circuit
*1: 470 when 4.43MHz crystal is used. 47 PAL/N or PAL PAL/M NTSC 0.47 15k 470p 30 29 28 15p 1.5k *1 27 15p 1.5k 26 15p 1.5k 25 24 23 22
Color difference Color difference output to 1H input from1H delay line delay line 0.01 1 21 1
- (B_Y) IN
X 443/358
SVCC
31 S GND
SECAM REF
- (R_Y) OUT
- (B_Y) OUT
- (R_Y) IN
X NTSC
APC
X 358
V OUT 20
V output
32 CIN
U OUT 19
U output
33 A PED Composite video input 4.7 34 CVBS/Y IN 0.47 35 ADRS
Y OUT 18
Y output
SGND2 17
SCP 16
SCP output
36 SCL I2C bus input/output 100 37 SDA 100 2.2k 100 1 3.3k 100p 39 H SYNC 220 4700p 0.47 40 V HOLD 38 V SYNC
H TIM 15
H TIM output
V TIM 14
V TIM output
V2 IN 13
1 V2 input 1 U2 input 1 Y2 input
U2 IN 12
V2 OUT
U2 OUT
Y2 OUT
ABLFILIN
CERA
J GND
330k 330 500kHz ceramic oscillator
IREF
1 0.01
2 8.2k 1
3 10k
4
5
6
7
8
9
10
V2 U2 Y2 output output otuput 0.01
ABL input
CPIN
47 +9V
A2025 ABLFIL voltage input. Connect to VCC when not used.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 16 -
CP IN
Y2 IN 11
AFC
JVCC
CXA2019AQ
Signals Used for Measurements
63.556s SIG-H1 4.7s 0.57V fH = 15.734kHz NTSC
64.0s SIG-H2 4.7s 0.57V fH = 15.625kHz PAL
62.563s SIG-H3 4.63s 0.57V fH + 250Hz
64.583s SIG-H4 4.78s 0.57V fH - 250Hz
3s SIG-H5 63.556s 3V
SIG-Y1
1.0V
1.43V SIG-Y2
4.8s 0.57V
- 17 -
CXA2019AQ
0.7V SIG-Y3
f = 3.0MHz or 100kHz
0.7V SIG-Y4
f = 8.0MHz or 100kHz
0.7V SIG-Y5 0.57Vp-p
f = 3.58MHz burst = 3.58MHz
SIG-Y6: f = 4.43MHz, burst = 4.43MHz for SIG-Y5 signal
SIG-C1 0.57V 180 168 348
0.48Vp-p
f = 3.58MHz burst = 3.58MHz
SIG-C2 0.57V 180 104 274
0.68Vp-p
f = 3.58MHz burst = 3.58MHz
- 18 -
CXA2019AQ
Description of Operation 1. Sync System The video signals (standard input level: 2Vp-p) input to Pins 38 and 39 are sync separated by the horizontal and vertical sync separation circuits. The resulting horizontal sync signal and the signal obtained by frequency dividing the 32fH-VCO output using the ceramic oscillator (frequency 500kHz or 503.5kHz) by 32 are phase compared, the AFC loop is constructed, and an H pulse (HTIM) synchronized with the H sync is output from Pin 15. The vertical sync signal is sent to the V countdown block where the most appropriate window processing is performed to obtain V sync timing information which resets the counter. A V pulse (VTIM) synchronized with the V sync is output from Pin 14. In addition, BGP, HBLK and VBLK are output from Pin 16 as SCP (sand castle pulse). 2. Y System There are two input systems. Composite video input (2Vp-p) 1 system Y/C separation input (2Vp-p) 1 system The Y signal (specified input level: 2Vp-p) input to Pin 34 passes through the subcontrast control, chroma trap, delay line, sharpness control, clamp and auto pedestal circuits, is gain adjusted by the YDRIVE circuit and is then output. The CXA2019AQ has a built-in chroma trap, enabling the video signal to be input directly. The trap frequency is automatically adjusted inside the IC. However, the trap frequency is affected by variations among the ICs, so fine adjustment through the I2C bus may be required. Because the f0 of the filter is not specified when the color killer function is operating, turn the trap OFF if there are any difficulties. The Y signal delay time can be varied in approximately 60ns increments through the I2C bus register (DELAY). In addition, when the C system TOT is ON, the Y signal delay time is increased by approximately 140ns to cope with the increase in the C system delay time caused by the TOT filter. The sharpness control is a delay line type and the sharpness f0 can be switched to 1.5MHz or 3MHz. 3. C System The CVBS or chroma signal (specified input level: burst level of 570mVp-p) selected by the internal video switch passes through the ACC, TOT, chroma amplifier and demodulation circuits, is demodulated into the R-Y and B-Y color difference signals, and is then inversed and output from Pins 23 and 24. However, during NTSC the signals are 6dB amplified by the internal DET switch and gain adjusted by the COLOR circuit. During PAL the signals are 6dB amplified by the 1H delay line, input to Pins 21 and 22, and gain adjusted by the COLOR circuit. Signals that have passed through the 1H delay line can also be input to the COLOR circuit during NTSC by using the I2C bus register (EXT COLOR). This provides comb filter effects. In addition, the color system (NTSC/PAL) and the subcarrier frequency (3.58MHz/4.43MHz) are automatically identified according to the input chroma signal, and the internal VCO and demodulation circuit, etc., are adjusted automatically. Furthermore, SECAM signals can also be automatically identified by connecting an external SECAM decoder to Pin 30. In this case, Pins 23 and 24 and the SECAM decoder color difference output are linked together directly, and one side goes to high impedance and the other side goes to low impedance according to the input chroma signal, and then they are input to the external 1H delay line. System identification can be set to automatic or forced mode by the I2C bus register. The color system is output to the status register. The pedestal levels of the U and V color difference signals are clamped by UPED and VPED, respectively, and then these signals are output. However, the DC of the video portion can be controlled by the I2C bus register, allowing the offset to be adjusted at the PINP processor input.
- 19 -
CXA2019AQ
4. YUV Reinput System The U and V color difference signals (output from the PINP processor) input to Pins 12 and 13 are clamped according to the pulse input to Pin 10, gain controlled by the U2 and V2 drive circuits, the DC of their video portion is controlled by the U2PED and V2PED circuits, and then these signals are output from Pins 6 and 7. This function allows adjustment of the white balance and black level of the PINP sub picture. In addition, the Y signal input to Pin 11 is clamped in the same manner, gain controlled by the Y2 drive circuit, and output from Pin 8. At this time, bright ABL with a polarity opposite that of the main picture ABL can be applied by inputting the main picture Y/C/J IC ABLFIL voltage to Pin 9. This allows fluctuation of the black level of the sub picture caused by the main picture ABL to be suppressed. This reverse polarity ABL can be turned ON and OFF and the gain and control curve center values can be set by the I2C bus register.
Notes on Operation * The CXA2019AQ does not perform the initial settings during power ON. This initial data should be input from a microcomputer. * Because the YUV signal output from the CXA2019AQ are DC direct connected, the board pattern must be designed consideration given to minimizing interference from around the power supply and GND. Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the bypass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also, locate the XTAL oscillator, ceramic oscillator and IREF resistor as near to the pin as possible, and do not wire signal lines near this pin. * Use lead type (HC-49/U type) for each XTAL oscillator. Confirm that there is no problem for capture range color response and others at resistors and capacitors as shown in Application Circuit. * Murata's Ceralock is recommended for ceramic oscillator. When using only for NTSC, 503.5kHz Ceralock; for NTSC/PAL, 500kHz Ceralock is recommended. * Use a resistor (such as a metal film resistor) with an error of less than 1% for the IREF pin. * For unused pins, leave them open.
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CXA2019AQ
Definition of I2C BUS Registers Slave Addresses Slave Receiver 9AH: ADRS = "High" 9EH: ADRS = "Low" Register Table x: Don't care, : Undefined Control Register Sub Address xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 COL SYSTEM COL LOOP bit7 bit6 bit5 HUE COLOR SHARPNESS SUB HUE CTRAPADJ Y DRIVE U PED U2 PED Y2 DRIVE U2 DRIVE V2 DRIVE X'TAL PIN SCP BGF V FREQ SCP BGR AFC SHP-f0 bit4 bit3 bit2 bit1 DPIC OFF HMASK SUB CONT SUB COLOR TRAP ON TOT ON FSC OUT CD MODE2 bit0 CV/YC CANAL
Slave Transmitter 9BH: ADRS = "High" 9FH: ADRS = "Low"
V PED V2 PED DC TRAN PRE OVER ABL CENT ABL OFF ABL DELAY EXT COLOR 1
Status Register bit7 H LOCK bit6 KILLER bit5 NT/PAL bit4 50/60 bit3 SECAM bit2 VCO-F bit1 bit0
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CXA2019AQ
Description of I2C BUS Registers Sub Address 0000 HUE (6): Hue control 0 = Flesh color appears red. 63 = Flesh color appears green. DPIC OFF (1): Y black expansion ON/OFF switch 0 = ON 1 = OFF CV/YC (1): Input selector switch 0 = CVBS input 1 = Y/C input Sub Address 0001 COLOR (6): Color control 0 = Minimum 63 = Maximum HMASK (1): Macrovision measures 0 = OFF 1 = ON CANAL (1): When this register is set to "1", the first and last 3H of the video are replaced by DC during YUV output. 0 = No video portion DC replacement 1 = DC replacement Sub Address 0010 SHARPNESS (4): Sharpness control 0 = Minimum 15 = Maximum SUB CONT (4): Sub contrast adjustment 0 = Minimum 15 = Maximum Sub Address 0011 SUB HUE (4): Hue center adjustment 0 = Flesh color appears red. 15 = Flesh color appears green. SUB COLOR (4): Color center adjustment 0 = Minimum 15 = Maximum Sub Address 0100 C-TRAP ADJ (4): Chroma trap f0 adjustment 0 = High 7 = Center 15 = Low AFC (2): AFC loop gain selector 0 = AFC loop gain high 1 = AFC loop gain medium 2 = AFC loop gain low 3 = AFC loop open, free-running mode - 22 -
CXA2019AQ
TRAP ON (1): Y system chroma trap ON/OFF 0 = OFF 1 = ON TOT ON (1): Chroma TOT filter ON/OFF 0 = OFF 1 = ON Sub Address 0101 Y DRIVE (5): Y output gain control 0 = -6.3dB 31 = +3.5dB SHP-f0 (1): Sharpness f0 selector 0 = 3MHz 1 = 1.5MHz FSC OUT (1): When this register os set to "1", the subcarrier frequency is output constantly from Pin 30. 0 = Output only during the VBLK interval in SECAM mode 1 = Constantly output CD MODE2 (1): V sync signal pull-in speed selector 0 = Standard 1 = High speed Sub Address 0110 U PED (4): DC control of pedestal portion of U output (for video) 0 = -8mV 7 = Center 15 = +10mV V PED (4): DC control of pedestal portion of V output (for video) 0 = -8mV 7 = Center 15 = +10mV Sub Address 0111 U2 PED (4): DC control of pedestal portion of U2 output reinput from PinP processor (for video) 0 = -35mV 7 = Center 15 = +40mV V2 PED (4): DC control of pedestal portion of V2 output reinput from PinP processor (for video) 0 = -35mV 7 = Center 15 = +40mV
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CXA2019AQ
Sub Address 1000
Y2 DRIVE (5): Y2 output gain control 0 = -4dB 31 = +2.8dB DC TRAN (3): DC transmission ratio setting 0 = Maximum (100%) 7 = Minimum (78%)
Sub Address 1001
U2 DRIVE (5): U2 output gain control 0 = -6.3dB 31 = +3.6dB PRE OVER (2): Sharpness preshoot/overshoot ratio setting 0 = 1:2 (PRE:OVER) 3 = 2:1 ABL OFF (1): ON/OFF for ABL applied to Y2 OUT 0 = ON 1 = OFF
Sub Address 1010
V2 DRIVE (5): V2 output gain control 0 = -6.3dB 31 = +3.6dB ABL CENT (2): ABL center voltage control 0 = Minimum 3 = Maximum ABL (1): ABL gain control 0 = Standard 1 = Low
Sub Address 1011
COL SYSTEM (2): Selects the color system identification method. 0 = Fixed to NTSC 1 = Fixed to PAL 2 = Fixed to SECAM 3 = Automatic identification X'TAL PIN (2): Selects the crystal. 0 = Fixed to Pin 26 (XNTSC) 1 = Fixed to Pin 27 (X358) 2 = Fixed to Pin 28 (X443/358) 3 = Automatic identification V FREQ (2): Inputs the V frequency during no signal. 0 = Force to 60Hz 1 = Force to 50Hz 2 = Automatic (previous status maintained) - 24 -
CXA2019AQ
DELAY (2): Allows the following delay times to be added to the Y signal. 0 = 0ns 1 = 60ns 2 = 120ns 3 = 180ns Sub Address 1100 COL LOOP (2): Specifies the identified color system when COL SYSTEM is set to automatic identification. 0 = PALM/PALN/NTSC (Pin 28 = PALN crystal, Pin 27 = PALM crystal, Pin 26 = NTSC crystal) 1 = PAL/SECAM/4.43NTSC/NTSC (Pin 28 = 4.43MHz crystal, Pin 27 = open, Pin 26 = NTSC crystal) 2 = PAL/SECAM (Pin 28 = 4.43MHz crystal, Pin 27 = open, Pin 26 = open) 3 = PALM/NTSC (Pin 28 = open, Pin 27 = PALM crystal, Pin 26 = NTSC crystal) SCP BGF (2): Controls the phase of the falling edge of the BGP in the SCP output. (0.4s per step) 0 = +0.4s 1 = Center 3 = -0.8s SCP BGR (2): Controls the phase of the rising edge of the BGP in the SCP output. (0.4s per step) 0 = +0.4s 1 = Center 3 = -0.8s EXT COLOR (1): Forcibly switches the DET switch input to external input (R-Y IN, B-Y IN). 0 = Switched by the NTSC/PAL identification results 1 = External input H LOCK (1): Returns whether or not the IC's H oscillator and the signal input to H SYNC are locked. 0 = Not locked 1 = Locked KILLER (1): Returns the color killer ON/OFF status. 0 = OFF 1 = ON NT/PAL (1): Identifies whether the input signal is NTSC or PAL and returns the results. 0 = NTSC 1 = PAL 50/60 (1): Returns the 50/60Hz identification results. 0 = 60Hz 1 = 50Hz SECAM (1): Identifies whether or not the input signal is SECAM and returns the results. 0 = Not SECAM 1 = SECAM VCO-F (1): Detects the input signal burst frequency and returns the results. 0 = 3.58MHz 1 = 4.43MHz - 25 -
CXA2019AQ
I2C BUS Register Initial Settings Register name HUE DPIC OFF CV/YC COLOR HMASK CANAL SHARPNESS SUB CONT SUB HUE SUB COLOR CTRAP ADJ AFC TRAP ON TOT ON Y DRIVE SHP-f0 FSC OUT CD MODE2 U PED V PED No. of bits 6 1 1 6 1 1 4 4 4 4 4 2 1 1 5 1 1 1 4 4 Initial setting 1FH 0H 1H 1FH 0H 0H 7H 7H 7H 7H 7H 1H 0H 0H FH 0H 0H 0H 7H 7H Description Center value DPIC ON Y/C input selection Center value Macrovision measures OFF CANAL OFF Center value Center value Center value Center value Center value Center value TRAP OFF TOT OFF Center value SHP = 3MHz FSC OUT OFF Standard Center value Center value EXT COLOR 1 0H Register name U2 PED V2 PED Y2 DRIVE DC TRAN U2 DRIVE PRE OVER ABL OFF V2 DRIVE ABL CENT ABL COL SYSTEM X'TAL PIN VFREQ DELAY COL LOOP SCP BGF SCP BGR No. of bits 4 4 5 3 5 2 1 5 2 1 2 2 2 2 2 2 2 Initial setting 7H 7H FH 0H FH 0H 1H FH 0H 0H 0H 0H 0H 0H 0H 1H 1H Description Center value Center value Center value Minimum value Center value Minimum value ABL OFF Center value Minimum value Standard NTSC Pin 26 selection 60Hz fixed Minimum value PAL M/N/NTSC Center value Center value Automatic identification
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CXA2019AQ
Example of Representative Characteristics
Outpt amplitude (black to white) [Vp-p]
YDRIVE characteristics
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 3 7 B Input: YIN 1.4Vp-p (black to white) Output: YOUT SUBCONT = 7 DCTRAN = 0 SHARPNESS = 7 F Data 13 17 1B 1F
SUBCONT characteristics
Difference from SUBCONT = 7 [dB]
3 2 1 0 -1 -2 -3 -4 1 3 5 Input: YIN 1.4Vp-p (black to white) Output: YOUT YDRIVE = F DCTRAN = 0 SHARPNESS = 7 7 Data 9 B D F
TRAP attenuation SHARPNESS characteristics
8 SHPSW = 0 6 4 SHARPNESS = 0 SHARPNESS = 7 SHARPNESS = F Input: YIN SWEEP Output: YOUT SUBCONT = 7 YDRIVE = F DCTRAN = 0 0 1 2 3 4 5 Frequency [MHz] 6 7 8 0
Attenuation [dB]
Gain [dB]
2 0 -2 -4 -6
-10
-20
-30
0
1
2345 Frequency [MHz] TRAPSW = 1 TRAPSW = 0 CTRAP ADJ = 9
6
7
DCTRAN characteristics
0
Transmission rate 98.9%
Black sink level [mV]
-50 -100 -150 -200 -250 Input: YIN 2Vp-p Output: YOUT SUBCONT = 7, YDRIVE = A SHARPNESS = 7 0 20 40 60 Input amplitude [IRE] 80 87.1% Transmission rate = (S - black sink level) /S S = 1.0Vp-p DCTRAN = 0 DCTRAN = 3 DCTRAN = 7
78.4% 100
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CXA2019AQ
AUTOPED characteristics
Output amplitude (black to white) [IRE]
100 80 60 40 20 0 Input: YIN FLAT Signal Outout: YOUT 100 IRE = 1.1Vp-p DCTRAN = 0, TRAP = 0 0 20 40 60 80 Input amplitude (black to white) [IRE] 100 2.5
COLOR control characteristics
Input: CVBS/YIN 75% COLORBAR 2Vp-p 2.0 Output: UOUT (YELLOW - BLUE) SUBCOLR = 7, SUBHUE = 7 1.5 HUE = 1F, TOT = 0 1.0 0.5 0
Output amplitude [Vp-p]
7
F
17
1F Data
27
2F
37
3F
SUBCOLOR control characteristics
Difference from SUBCOLOR = 7 [dB]
4 2 2 0
TOT characteristics
TOT = OFF
Attenuation [dB]
-2 -4 TOT = ON -6 -8 -10
0 -2 -4 -6 Input: CVBS/YIN 75% COLORBAR 2Vp-p Output: UOUT (YELLOW - BLUE) 1 3 5 7 Data 9 B D F
-12
-1
-0.5 0 Difference from 3.579545MHz [MHz]
0.5
Difference from video blac level for output [mV]
UPED/VPED control characteristics
10 1.6
R2/V2DRIVE control characteristics
U2DRIVE V2DRIVE
Output amplitude [Vp-p]
1.4 1.2 1.0 0.8 0.6 0.4 3
0 Input: No signal Output: UOUT/VOUT SUBCOLOR = 7 COLOR = 1F -10 1 3 5 7 Data 9 B D F
Input: U2IN/V2IN 1Vp-p PULSE positive polarity Output: U2OUT/V2OUT 7 B F Data 13 17 1B 1F
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CXA2019AQ
Difference from video black level for output [mV]
R2/V2PED control characteristics
Output amplitude (black to white) [Vp-p]
60 40 20 0 -20 -40 Input: No signal Output: U2OUT/V2OUT 1 3 5 7 Data 9 B D F U2PED V2PED 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4
Y2DRIVE control characteristics
Input: Y2IN 1Vp-p PULSE (positive polarity) Output: Y2OUT ABLOFF = 1 3 7 B F Data 13 17 1B 1F
ABL control characteristics
300
Output DC variation [mV]
250 200 150 100 50 0 -50 0 1
Input: Y2IN no signal Output: Y2OUT RYDRIVE = F
ABL = 1/ABLCENT = 3 ABL = 0/ABLCENT = 0 ABL = 0/ABLCENT = 3 2 3 4 5 6 7 ABLFILIN voltage [V] 8 9
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CXA2019AQ
Package Outline
Unit: mm
40PIN QFP (PLASTIC)
9.0 0.4 + 0.4 7.0 - 0.1 30 21
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1
31
20
A
40 1 0.65 + 0.15 0.3 - 0.1 + 0.15 0.1 - 0.1
11
10 0.12 M
0.5 0.2
(8.0)
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.2g
DETAIL A SONY CODE EIAJ CODE JEDEC CODE QFP-40P-L01 QFP040-P-0707
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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